The present invention relates to the field of electrochemical deposition, and in particular to a method of forming a metal seed layer by electroplating.
The performance characteristics and reliability of integrated circuits have become increasingly dependent on the structure and attributes of the vias and interconnects which are used to carry electronic signals between semiconductor devices on integrated circuits or chips. Advances in the fabrication of integrated circuits have resulted in increases in the density and number of semiconductor devices contained on a typical chip. Interconnect structure and formation technology has lagged behind these advances, however, and is now a major limitation on the signal speed of integrated circuits.
Current techniques for forming vias and interconnects begin with preparation of the semiconductor wafer surface by formation of an interlevel dielectric layer (ILD), typically silicon dioxide. A mask may then be applied to pattern the deposition of the interconnect material on the wafer in the desired manner. Another typical process is to plate the interconnect material onto the surface of the wafer to a depth sufficient to fill the vias, followed by planarization to achieve the desired interconnect pattern.
Typically the preferred metal for use in the construction of integrated circuit interconnects has been aluminum. Aluminum is widely used because it is inexpensive, relatively easy to etch, and adheres well to ILDs such as silicon dioxide. Disadvantages of aluminum include significant electromigration effects, susceptibility to humidity-induced corrosion, and the tendency to xe2x80x9ccold creepxe2x80x9d. xe2x80x9cCold creepxe2x80x9d is a process that creates cracks or spaces between the interconnect layer and the ILD due to large variances in the coefficient of thermal expansion between the two materials.
The disadvantages of aluminum interconnects have become more pronounced as the geometry of integrated circuits continues to shrink. Chip designers have attempted to utilize different materials to construct an interconnect system having the chemical and mechanical properties which will complement and enhance smaller and faster circuit systems. The ideal interconnect material is inexpensive, and has low resistivity, minimal electromigration effects, high corrosion resistance, and a similar coefficient of thermal expansion to the ILD and substrate material. Metals possessing these properties include gold, silver, and copper, and research has generally focused on these three metals as new via and interconnect materials.
Copper is the most attractive material for use in integrated circuits because of its desirable chemical and mechanical properties. It is an excellent conductor with a resistivity of 1.73 microOhms per centimeter, is inexpensive, and is easily processed. Copper also has fewer electromigration effects than aluminum and can therefore carry a higher maximum current density, permitting a faster rate of electron transfer. The high melting point and ductility of copper produce far less cold creep during the semiconductor fabrication process than many other metals, including aluminum.
Although copper has many favorable characteristics, it also has disadvantages that may create fabrication problems for chip designers. Copper is soluble in silicon and most common ILDs, and exhibits a high rate of diffusion at temperatures associated with integrated circuit manufacturing. This diffusion can result in the creation of intermetallic alloys which can cause malfunctioning of the active semiconductor devices. In addition, copper exhibits poor adhesion to silicon dioxide which can result in broken connections and failure of electrical contacts.
Use of an intermediate barrier layer between the ILD and the copper interconnect permits the successful use of copper in a silicon-based integrated circuit. The barrier layer serves to eliminate the diffusion that would otherwise occur at the copper-ILD junction, and thus prevents the copper from altering the electrical characteristics of the silicon-based semiconductor devices. Such barrier layers are well known in the art and may be formed of a variety of transition metals, transition metal alloys or silicides, metal nitrides, and ternary amorphous alloys. The most common barrier layer materials in use are titanium, tantalum, and tungsten alloys due to their demonstrated ability to effectively reduce copper diffusion.
Deposition of a metallization layer generally occurs through one of the following techniques: chemical vapor deposition (CVD); physical vapor deposition (PVD), also known as sputtering; or electrochemical deposition. CVD involves high temperatures which can lead to cold creep effects and an increased chance of impurity contamination over other methods, and sputtering has problems yielding sufficient step coverage and density at small line widths. Electrochemical deposition, however, offers a more controlled environment to reduce the chance of contamination, and a process that takes place with minor temperature fluctuations. Electrochemical deposition provides more thorough coverage, fewer physical flaws, and reduces separation between the layers.
There are several known electrochemical deposition processes used to form copper interconnects onto barrier layers, each having various disadvantages. Direct deposition of copper onto the barrier layer typically results in porous films with poor adhesion and inconsistent densities. Annealing of the deposited copper at low temperatures may be performed to improve adhesion, but it increases cold creep effects and fails to provide a consistently dense copper structure. A copper seed layer may be formed over the barrier layer by CVD or PVD to produce an adhesive surface, and then electrochemical deposition may be carried out on the seed layer. This method involves multiple steps and increases production costs by requiring several different types of machines to form each interconnect layer.
What is needed, therefore, is a simple and inexpensive method of forming a metal seed layer that requires only a minimum number of steps for its production.
The present invention provides a method of forming a metal seed layer, preferably a copper layer, for subsequent electrochemical deposition. The metal seed layer is formed by the oxidation-reduction reaction of a metal salt or complex such as copper sulfate in acid solution, with a reducing agent such as elemental silicon that is present in a layer on the substrate to be plated. Preferably the reducing agent is present in a sacrificial layer on the substrate. The method is particularly suited to forming metal interconnects for semiconductor devices, because the metal seed layer and the plating of the interconnect itself may be combined into a single-bath operation.
Additional advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.